The present embodiments relate to digital circuits and are more specifically directed to a first-order noise generator.
Noise generator output signals are used in various electronic device applications. As one application and detailed later, such a generator may provide a noise signal having a desired frequency profile (i.e., shaped noise) for use in an electronic device, such as in a sigma-delta converter. In this and other applications, various design criteria are often established in connection with implementing the noise generator, and indeed these criteria often apply to other circuitry associated with the application. For example, one criterion is to minimize the amount of power consumed by a device. As other examples, device size, complexity, and cost all should be minimized. As still another example with respect to the various signal generators, a certain frequency response is desired. Particularly in the present context of a first-order noise signal generator, preferably the response curve, over a desired range of frequencies, is such that the response curve changes by 10 dB per every order of magnitude of frequency of interest, where each order of frequency is sometimes referred to as a “decade;” thus, the goal is a frequency response change of 10 dB/decade for a first-order response. The preceding goals have been met to a certain extent in the prior art by implementing a first-order decay signal generator using a number of linear feedback shift registers (“LFSRs”) in a single implementation, as further detailed below.
By way of background first to an individual LFSR, FIG. 1 illustrates a single LFSR designated generally at 10. LFSR 10 has N bit positions B0 through BN-1, each for storing a binary value of 0 or 1. As a shift register, the device operates in a cycle, typically in response to a clock (not shown), to shift the content of each bit position in a same direction and into a respective adjacent bit position, where the content in one end (e.g., at BN-1) is shifted out of the register and the content at the other end (e.g., B0) receives a new input value. Thus, in this example and for sake of uniform discussion in this document, a shift is shown to be from left to right, although the opposite case most certainly may be alternatively implemented by one skilled in the art. In an LFSR, the bit content at selected bit positions (“SBPs”) of the register are combined into a function, shown as function ƒ{SBPs} and designated at 20 in FIG. 1. The output of function ƒ{SBPs} is also input into the register's input bit, which in the present example is bit position B0. Thus, in a given cycle, function ƒ{SBPs} is determined, and while each of bit positions B0 through BN-2 shifts its content rightward to the next adjacent bit and BN-1 shifts its content out of register 10, the result of function ƒ{SBPs} is provided as an input to bit position B0. This determination of function ƒ{SBPs} and its provision as an input is the feedback function of the LFSR. Note that the function ƒ{SBPs} may be determined in various forms, and typically it is implemented as a logical XOR of the SBPs, which are also sometimes referred to as taps, in a given order. The particular positions chosen as the SBPs as well as the exact choice of function ƒ{SBPs} vary and may be determined by one skilled in the art from various known or ascertainable resources. Two uses of the contents of LFSR 10 of FIG. 1 are noted with respect to the prior art, as separately described below.
In a first prior art use of LFSR 10, the entire sequence of bits, B0 through BN-1 (which may be designated as [B0:BN-1]) may be used as a pseudorandom code generator. Such an application is desirable in telecommunication applications, or elsewhere, where a code is desired that has good auto and cross-correlation properties. When such an application is implemented, the sequence of [B0:BN-1] as it changes for each cycle of operation provides in effect a white or nearly-white noise signal. To illustrate this aspect, FIG. 2 depicts a plot of the FFT of such a sequence over time, for an example of N=16 and for use of the SBPs of bit positions B3, B8, B14, and B15, and at a clocking rate of 40 MHz of LFSR 10. As can be readily appreciated, across the depicted frequency spectrum there is a 0 dB response, demonstrating therefore the above-described white noise signal.
A second prior art use of LFSR 10 is now described with reference to FIG. 3. FIG. 3 illustrates a first-order noise generator 30, that is, one that produces an output signal having a decay on the order of 10 dB/decade. Generator 30 includes a number M of LFSRs, each of the general form of LFSR 10 in FIG. 1 and, thus, for sake of reference, shown in FIG. 3 as LFSR 100, 101, and so forth through 10M-1. While not explicitly shown, note also that each different LFSRx in FIG. 3 may use different taps as compared to the other LFSRs in generator 30. The output of a same bit position of each LFSR is concatenated into an M-bit register 40, thereby providing a value with bits V0 through VM-1; for sake of example, that same bit position in FIG. 3 is shown as the rightmost position (corresponding to position BN-1) in FIG. 1. Value [V0:VM-1] is connected as an input to a first order high pass filter 45, which in response provides an output to a twos complement analyzer 50, the output of which provides a first-order noise signal, FON. The operation of each LFSR 10x in generator 30 is as described in connection with FIG. 1, operating therefore in parallel and in a single cycle to each provide a respective value bit, Vx, to register 40. In response, twos complement analyzer 50 interprets the output of first order high pass filter 45 as a twos complement number, and thereby outputs its equivalent such as a signed number as FON. Thus, value [V0:VM-1] changes for each cycle of operation of the LFSRs 100 through 10M-1. With this operation and the successive changes in value [V0:VM-1] as well as the corresponding changes in FON, a first-order response is generated, that is, the changes in FON provide a 10 dB/decade decay if examined in the frequency domain.
While the preceding applications have proven useful in various implementations, recall that design criteria seek to reduce device size, complexity, power consumption, and cost. Given these goals as well as others that may be ascertained by one skilled in the art, there arises a need to improve upon the prior art, as is achieved by the preferred embodiments described below.